Design and implementation for image reconstruction of CompressiveSensing using FPGA

A novel single pixel camera system has been introduced to overcome the current limitation and challenges of traditional focal plane arrays. This new hardware system mainly employs one photo-sensing element/pixel and a digital micromirror device (DMD). By consideration of a new mathematical theory and algorithms of compressive sampling, we can reconstruct images based on the measurement results of the photo-sensing element. However, the development reminds challenge. Since large amount of data is accessed and the inherent delay of instruction cycle within transporting data on the DMD, it makes real-time processing of image recovery difficult. Conventionally, the pattern data was transported to DMD from PC through USB interface. Since the USB interface limited the data transfer speed, the total time of signal collection and image reconstruction was about 30 minutes. In this paper, FPGA is used to transport data from SDRAM to control the DMD, and at the same time, the signal of the photo-sensing element is acquired. As a result the control of the DMD can be improved and imaging processing time can be reduced. The development includes various components such as SDRAM interface, FIFO Data buffer, ADC interface, USB interface and DMD control interface. Comparing with the method of transporting data through PC, the time for image recovery is greatly reduced.