Test solutions for nanoscale Systems-on-Chip: Algorithms, methods and test infrastructure

With technologies shrinking and design complexity increasing, it becomes crucial that embedded in chip test and repair solutions keep up with the advances in order to consistently provide superior chip quality and yield optimization. The embedded test approaches developed for designs done a few years ago are not sufficient for today´s designs, which are bigger, faster, hierarchical and much more sensitive to area, timing and power. Similarly, the embedded test solutions developed e.g. for 28-nm technology nodes will not deliver the same level of test quality, diagnosis accuracy and repair efficiency for 14-nm technology nodes, as defects and failure mechanisms change with process technologies shrink.