DocumentCode :
67321
Title :
Flexible and low-complexity bit-reversal scheme for serial-data FFT processors
Author :
Chu Yu
Author_Institution :
Dept. of Electron. Eng., Nat. Ilan Univ., Yilan, Taiwan
Volume :
51
Issue :
4
fYear :
2015
fDate :
2 19 2015
Firstpage :
328
Lastpage :
330
Abstract :
A simple yet flexible bit-reversal hardware scheme applicable to variable-length fast Fourier transform (FFT) processors to facilitate the continuous flow of serial data is presented. The proposed design employs a length-N two-port register file (N is the processing size of the FFT), and a simple address generator to perform variable-length bit-reversal operations on the input or output of the FFT processor. This enables the conversion of bit-reversed data to the natural order. The proposed scheme is superior to the existing technologies because of its ability to process a continuous-flow input sequence and its applicability to variable-length FFT processors without the need for a shuffling mechanism on the input and output memory ports. The proposed design is particularly suitable for applications involving bit-reversal operations on large-point FFT processors.
Keywords :
fast Fourier transforms; integrated memory circuits; address generator; continuous-flow input sequence; flexible bit-reversal scheme; length-N two-port register file; low-complexity bit-reversal scheme; serial-data FFT processors; variable-length bit-reversal operations; variable-length fast Fourier transform processors;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2014.3270
Filename :
7042435
Link To Document :
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