DocumentCode :
67536
Title :
PDN Impedance Modeling for Multiple Through Vias Array in Doped Silicon
Author :
Guang-Xiao Luo ; Er-Ping Li ; Xing-Chang Wei ; Xiang Cui ; Ran Hao
Author_Institution :
State Key Lab. of Alternate Electr. Power Syst. with Renewable Energy Sources, North China Electr. Power Univ., Beijing, China
Volume :
56
Issue :
5
fYear :
2014
fDate :
Oct. 2014
Firstpage :
1202
Lastpage :
1209
Abstract :
The power distribution network (PDN) impedance of 3-D-through silicon vias (TSVs) interposer layer is modeled by considering the metal-oxide-semiconductor (MOS) structure effects. The Lambert W function is proposed to simulate the change of depletion width with the bias voltage in the static field, and the high-frequency MOS capacitance is obtained while considering the charges at the semiconductor-insulator interface. Furthermore, based on the depletion width and the insulating dielectric layer assumption, the electrical model of power-ground TSVs pair is presented by combining the MOS capacitance with TSVs parasitic RLGC (resistance-inductance-capacitance-conductance). Finally, the PDN impedance characteristics of the 3-D-IC integrated system with multiple TSVs are performed by using the proposed multitransmission line and model reduction methods, and the importance of the capacitance is presented.
Keywords :
elemental semiconductors; integrated circuit interconnections; integrated circuit modelling; silicon; three-dimensional integrated circuits; 3D integrated circuit; 3D-through silicon vias; Lambert W function; PDN impedance modeling; Silicon; electrical model; high-frequency MOS capacitance; insulating dielectric layer assumption; interposer layer; metal-oxide-semiconductor structure effects; model reduction; multitransmission line; power distribution network; power-ground TSV pair; semiconductor-insulator interface; Arrays; Capacitance; Integrated circuit modeling; Mathematical model; Silicon; Substrates; Through-silicon vias; Insulating dielectric layer assumption; Poisson equation; metal-oxide-semiconductor (MOS) capacitance; through silicon vias (TSVs);
fLanguage :
English
Journal_Title :
Electromagnetic Compatibility, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9375
Type :
jour
DOI :
10.1109/TEMC.2014.2312356
Filename :
6784123
Link To Document :
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