Title :
Three-dimensional integrated circuits with NFET and PFET on separate layers fabricated by low temperature Au/SiO2 hybrid bonding
Author :
Goto, Misako ; Hagiwara, Kazuki ; Iguchi, Yoshinori ; Ohtake, H. ; Saraya, Takuya ; Higurashi, Eiji ; Toshiyoshi, Hiroshi ; Hiramoto, Toshiro
Author_Institution :
NHK Sci. & Technol. Res. Labs., Tokyo, Japan
Abstract :
We report the first demonstration of 3D ICs formed by the direct bonding of NFET and PFET prepared on separate layers. Hybrid bonding of Au/SiO2 at a low temperature of 200°C allows direct connection of NFETs and PFETs after completion of the FET process without area penalty. We have demonstrated successful operation of a 3D CMOS inverter bonded through 3-μm-diameter Au electrodes and a ring oscillator (RO) of 101 stages to show the feasibility of a novel 3D integration toward high-density ICs.
Keywords :
CMOS integrated circuits; field effect transistors; gold; integrated circuit bonding; invertors; silicon compounds; three-dimensional integrated circuits; 3D CMOS inverter; 3D ICs; Au-SiO2; FET process; NFET; PFET; electrodes; low temperature hybrid bonding; ring oscillator; temperature 200 degC; three-dimensional integrated circuits; Bonding; CMOS integrated circuits; Electrodes; Gold; Integrated circuit interconnections; Inverters; Three-dimensional displays;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716519
