Title :
Concurrent design analysis of A 8500V ESD-protected SP10T switch in SOI CMOS
Author :
Wang, X. Shawn ; Xin Wang ; Zongyu Dong ; Fei Lu ; Li Wang ; Rui Ma ; Chen Zhang ; Wang, Aiping ; Yue, C. Patrick ; Wang, Dongping ; Joseph, Alvin
Author_Institution :
Dept. of ECE, Univ. of California, Santa Barbara, Santa Barbara, CA, USA
Abstract :
SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].
Keywords :
CMOS integrated circuits; electrostatic discharge; silicon-on-insulator; switches; ESD-protected SP10T switch; SOI CMOS; SPMT-ESD interaction; codesign analysis; concurrent design analysis; high ESD protection; high linearity SP10T; single-pole multiple-throw switch; voltage 0 V to 700 V; voltage 8500 V; CMOS integrated circuits; Degradation; Electrostatic discharges; Field effect transistors; GSM; Linearity; Logic gates;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716560
