DocumentCode :
675589
Title :
NW-TFET analog performance for different Ge source compositions
Author :
Agopian, Paula G. D. ; Dos Santos, Sara D. ; Neves, F.S. ; Martino, Joao Antonio ; Vandooren, A. ; Rooyackers, R. ; Simoen, Eddy ; Claeys, Cor
Author_Institution :
LSI, Univ. of Sao Paulo, Sao Paulo, Brazil
fYear :
2013
fDate :
7-10 Oct. 2013
Firstpage :
1
Lastpage :
2
Abstract :
The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain (AV) due to their better output conductance (less drain electric field penetration than for 46%). The Si source NW-TFET presented the worst analog behavior at lower gate bias. However, when VGS increases, smaller is its AV degradation making it equal or better than the value obtained for SiGe source devices, since in the former the Trap Assisted Tunneling (TAT) is predominant. The peculiar NW-TFET low frequency noise behavior is also presented.
Keywords :
electric admittance; elemental semiconductors; field effect transistors; germanium; nanoelectronics; nanowires; semiconductor heterojunctions; silicon; tunnel transistors; Ge; Ge source compositions; NW-TFET analog performance; Si; bandgap; drain electric field penetration; heterojunction vertical nanowire tunnel FETs; intrinsic voltage gain; low frequency noise behavior; output conductance; transconductance; trap assisted tunneling; Degradation; Logic gates; Noise; Passivation; Silicon; Silicon germanium; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
Type :
conf
DOI :
10.1109/S3S.2013.6716561
Filename :
6716561
Link To Document :
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