Title :
SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI
Author :
Suraci, Gregory ; Giraud, Bastien ; Benoist, Thomas ; Makosiej, Adam ; Thomas, O.
Author_Institution :
LETI, CEA, Grenoble, France
Abstract :
This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI) technology. The proposed Mixed Single Well (Mixed-SW) design concept enables a major speed improvement over a wide voltage range with no standby power penalty, as compared to a regular Vt (RVT) design. The simulation results of a Mixed-SW dual-port SRAM row decoder show 16% and 57% propagation delay reduction at 1V and 0.5V, respectively. The gain obtained at RVT design standby power is enabled by the wide range N-Well back biasing.
Keywords :
SRAM chips; decoding; elemental semiconductors; integrated circuit design; silicon; silicon-on-insulator; RVT design; Si; UTBB-FDSOI; mixed single well design; mixed-SW dual-port SRAM row decoder design; portable device; propagation delay reduction; regular Vτ design; size 28 nm; ultrathin body-buried oxide fully-depleted silicon-on-insulator; voltage 0.5 V; voltage 1 V; wide range N-well back biasing; Decoding; Logic gates; MOS devices; Performance gain; Power demand; Propagation delay; Random access memory;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716580
