StML: Bridging the gap between FPGA design and HDL circuit description

FPGA circuit implementation is a unidirectional and time-consuming process. Existing approaches like the incremental synthesis try to shorten it, but still need to execute the whole flow for a changed circuit partition. Other approaches circumvent process stages by providing bidirectional mappings between their results. In this paper we propose an approach to provide a bidirectional link between an FPGA design and its HDL code. This link enables the circumvention of the most time-consuming stages (synthesis, mapping, placing, routing) of the FPGA circuit implementation. We implemented our approach in a Java-based EDA tool library, called Static Mapping Library (StML). We demonstrate its applicability by means of hardware debugging and an RTL-based injection of permanent faults, built on top of the StML. Experimental results illustrate that a mapping coverage between 98.5%-100.0% can be obtained, which substantiates the feasibility of this approach. Further experiments illustrate a controllable tradeoff between area overhead, circuit granularity and mapping granularity. With the finest mapping granularity, the area overhead has been between 1.8% and 60.2% for RTL-based circuits. The speedup of the proposed fault injection method has been estimated to be up to 6x for the tested circuits.