On the operational features and performance of a memristor-based cell for a LUT of an FPGA

This paper presents the detailed analysis of a memristor-based cell for a Look-Up Table (LUT) of a FPGA. The basic operational properties of this memristor-based cell are considered in depth. It shows that different from previous schemes, the ringing phenomenon of the so-called normalized state parameter does not affect data integrity. An extensive simulation based analysis of the two basic memory operations (READ and WRITE) and the corrective operation (RESTORE) is provided to show its substantial advantages. Moreover, the impact of varying different features of the memristor (range and dimension) and the feature size of the NMOS is evaluated for the resistive assessment at cell-level to show substantial improvements in terms of energy dissipation and READ/WRITE times.