Effect of spacers on Si tunneling field effect transistor with P-N-I-N structure

Author

Dinda, Satya Gopal ; Ghosh, Bablu

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, Kanpur, India

fYear

2013

fDate

13-15 Dec. 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents an improved novel TFET device architecture which exploits electric field modulation by introducing low-k spacers combined with source/drain electrode contact placed at top and bottom side of the designed device. Numerical simulation of the optimized device architecture shows high on current, reduced subthreshold swing and good ambipolar behaviour. The structure under investigation shows 5 times increase in on current level compared to the other structure which do not use spacers.

Keywords

electrodes; field effect transistors; numerical analysis; tunnel transistors; P-N-I-N structure; Si; TFET device architecture; ambipolar behaviour; electric field modulation; high on current reduced subthreshold swing; low-k spacer effect; numerical simulation; source-drain electrode contact; tunneling field effect transistor; Doping; Electric fields; Logic gates; Semiconductor process modeling; Silicon; Tunneling; Ambipolar Current. TCAD; Band to Band Tunneling; Subthreshold Slope;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2013 Annual IEEE

Conference_Location

Mumbai

Print_ISBN

978-1-4799-2274-1

Type

conf

DOI

10.1109/INDCON.2013.6725856

Filename

6725856