A VLSI architecture for arrhythmia detection and its implementation on FPGA

This paper presents a VLSI based design of high speed and area efficient distributive arithmetic discrete wavelet transform for arrhythmia detection and its FPGA implementation. The main focus of the paper is to detect the QRS complex in the ECG signal and to identify the time and frequency variations. By comparing these variations with that of the variations in the normal ECG waveform one may reach to a conclusion if the patient is suffering from arrhythmia or not. The distributive arithmetic discrete wavelet transform is also used for compressing the ECG signal so as to reduce the amount of space required for storage. Results have been successfully verified by using a combination of MATLAB, MODELSIM softwares and is successfully implemented on the FPGA so that it can itself work as a DSP processor for ECG analysis and arrhythmia detection.