A CMOS LNA Using a Harmonic Rejection Technique to Enhance Its Linearity

In this study, we design a differential low-noise amplifier (LNA) using a 0.18- μm RF CMOS process. To improve its linearity, we propose a harmonic rejection technique using RC feedback at the gain stage. The third harmonic component of the drain node of the common-gate transistor is fed back to the source node of the common-gate transistor to restrict the generation of the third harmonic component at the output of the LNA. To verify the feasibility of the proposed technique for a linear amplifier, we designed a typical LNA and the proposed LNA in an identical process and with the same design parameters apart from the feedback loop of the proposed LNA. The measured improvement of the input-referred P1 dB of the proposed LNA is approximately 3 dB compared to that of the typical LNA. From these measured results, we successfully prove the feasibility of the proposed linearization technique.