Real time implementation of digital filter on control strategy of DSTATCOM for load compensation under distorted utility condition

The Distribution STATic COMpensator (DSTAT-COM) has proved to be a useful custom power device to eliminate harmonic components and to compensate reactive power for balanced /unbalanced linear/nonlinear loads. This paper presents a novel control strategy to calculate the reference compensation current of three phase DSTATCOM under distorted utility condition at instantaneous state. In this proposed approach digital FIR filters with cut off frequency 25,100 Hz of direct form structure have been implemented on FPGA to make the process faster. The performance of the system simulated in Matlab Platform and evaluated considering the source current total harmonic distortion. The VHDL design has been implemented using ISE10.1 tool from Xilinx. This is tested on a board with hardware configuration such as FPGA - XC2VP4 with on chip PowerPC-405 Processor, ADC AD9240-14 bit 10MSPS analog input channel, DAC AD7541-12-bit of conversion time-10Ons with System clock 40 MHz.