A restricted dynamically reconfigurable architecture for low power processors

Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-efficient processors that map a target program´s hot path to a reconfigurable datapath. In this paper, we propose a Control-Flow Driven Data-Flow Switching (CDDS) variable datapath architecture for embedded applications that demand extremely low power consumption in a wide range of uses. This architecture is characterized by following two features: (1) achieving both flexibility and low energy consumption by limiting the scope of the dynamic reconfiguration, (2) realizing smooth migration from the existing architecture by mapping the existing instruction sequence to the datapath. Preliminary evaluation on small programs have revealed that the CDDS accelerator achieves approximately 3 to 6 times the performance/power improvements, compared to a base processor.