DocumentCode :
680093
Title :
Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform
Author :
Singla, Garbi ; Tobajas, F. ; de Armas, V.
Author_Institution :
Dept. of Electron. Eng. & Control, Univ. of Las Palmas de Gran Canaria (ULPGC), Las Palmas de Gran Canaria, Spain
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
1
Lastpage :
6
Abstract :
MultiProcessor Systems-on-Chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. For that purpose, Networks-on-Chip (NoC) are proposed as a promising solution to interconnection in MPSoCs for reasons of efficiency and scalability. In this scenario, the need to develop low-cost platforms to support NoC-based SoC design and verification is growing. In this work, the design of a low cost NoC-based MPSoC platform and its application to a video enhancement algorithm based on Super Resolution (SR) are presented. To validate the designed hardware platform, an optimized SR algorithm is mapped on the Processing Elements (PE) of the NoC-based SoC platform. Finally, the performance is characterized from experimental measurements according to the type of application, as well as the number of PE used.
Keywords :
image enhancement; image resolution; integrated circuit design; network-on-chip; video signal processing; PE; SR algorithm; hardware platform; low-cost NoC-based MPSoC platform; multiprocessor systems-on-chip; networks-on-chip-based design; processing elements; real-life embedded applications; video enhancement algorithm; video superresolution algorithm; Embedded systems; Field programmable gate arrays; Hardware; Memory management; System-on-chip; Video sequences; NIPSoC FPGA; Network-on-Chip; SuperResolution; System-on-Chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4799-2078-5
Type :
conf
DOI :
10.1109/ReConFig.2013.6732337
Filename :
6732337
Link To Document :
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