Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform

MultiProcessor Systems-on-Chip (MPSoC) are required to fulfill the performance demand of modern real-life embedded applications. For that purpose, Networks-on-Chip (NoC) are proposed as a promising solution to interconnection in MPSoCs for reasons of efficiency and scalability. In this scenario, the need to develop low-cost platforms to support NoC-based SoC design and verification is growing. In this work, the design of a low cost NoC-based MPSoC platform and its application to a video enhancement algorithm based on Super Resolution (SR) are presented. To validate the designed hardware platform, an optimized SR algorithm is mapped on the Processing Elements (PE) of the NoC-based SoC platform. Finally, the performance is characterized from experimental measurements according to the type of application, as well as the number of PE used.