Hardware co-simulation of Walsh sequences for 3G Software Defined Radio

This paper aims the hardware co-simulation of parameterized Walsh code with classical counter architecture using MATLAB SIMULINK based Xilinx System Generator software tools. This is an implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions such as Rademacher functions and Walsh functions. We investigate 64-orthogonal set for 3G standard such as CDMA2000 and WCDMA with classical binary counter architecture and found that it consumes 28 mW and 130 mW at 100 MHz and 500 MHz respectively. The target FPGA device is Virtex-5 (XC5VLX50T-1ff1136).