Strategies of cost reduction and high performance on a-Si:H/c-Si heterojunction solar cells: 21% efficiency on monolike substrate

In the actual PV context, it is mandatory to address cost reduction maintaining very high efficiency to be competitive. In the case of amorphous/crystalline heterojunction technology (HET), cost pareto is driven by Silver consumption by screen printing pastes followed by Silicon substrate. One option is to substitute Silver by Cu plating. Regarding material costs, monocrystalline (i.e, Czochralski (Cz) or Float-Zone (FZ)) silicon wafers might be also replaced by the so-called monolike or quasi-mono silicon in order to reduce the cost of the required high quality substrates In this paper, we show the latest results integrating both options on HET solar cell developments. Monolike processes have been optimized to reach excellent bulk quality, leading to effective carrier lifetimes over 1ms and implied open circuit voltage over 720mV comparable to Cz silicon. The combination with a Cu-plating metallization on an optimized structure, INES has reached over 21% efficiency on large area devices.