Optimization of scheduling mode for conflicts across the block

Instruction scheduling helps to hide pipeline delays and cache latencies in VLIW architectures, whose performance heavily depends on the compiler optimization techniques. However, the instruction conflicts across blocks also need to be taken into account while compiling. In order to solve this problem with as less performance loss as possible, the paper presents a general framework which hides the delay of conflicts in three different aspects. The experiments indicate that the proposed algorithms have achieved the goal of solving the conflicts with less cost in performance.