Combining fault tolerance and self repair in a virtual TMR scheme

With decreasing minimum feature size, nano-electronic circuits and systems exhibit an increasing variety of defect and fault mechanisms. Their rising sensitivity to radiation- and coupling induced single and multiple event upsets is one problem, new or enhanced aging processes that may lead to early-lifetime failures pose another threat. The compensation of transient fault effects is a well explored are of science, while repair technologies that tackle permanent faults have so far found a broad acceptance only for embedded memories and for FPGA-based systems. However, specifically such methods and architectures are of great practical importance for the compensation of early-lifetime failures. The combination of fast error compensation and repair mechanisms is even more challenging, since also aspects of minimum power consumption become important in many areas of application.