Design and application of a digital frequency discriminator constructured by two counters

For solving the problems that exist in the design of digital frequency discriminator (DFD) of an all-digital phase-locked loop (ADPLL), a digital frequency discriminator constructured by two counters is proposed. It is designed firstly by using electronic design automation (EDA) technology, and then is applied to the design of ADPLLs. The register transfer level (RTL) circuit schematic and simulation diagram of the frequency discriminator are both given, and the system simulation of an ADPLL is then implemented in the paper. Experimental results show that the proposed DFD is adapted accurately and sensitively to the frequency variation of both the input and feedback signals, and gives corresponding clear frequency polarity signal. For those ADPLLs with this proposed DFD, the design complexity will be obviously reduced, the capturing speed of the loop frequency be significantly increased, and system performance be clearly enhanced. It can also be applied to the design of system on chip (SOC) phase-locked loop.