A novel embedded design using High Performance and Low Leakage 6T SRAM Cell based on word decoding scheme at 90 nm technology

Author

Sehgal, Gaurav ; Yadav, Nanda Kishore

Author_Institution

EZHIMALA, India

fYear

2013

fDate

12-14 Dec. 2013

Firstpage

23

Lastpage

27

Abstract

Data retention and leakage are among the major areas of concern in contemporary CMOS technology. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines. The paper deals with the designing and analysis of 6T Static Random Access Memory (SRAM) cell focusing primarily over Leakage and delay. The results obtained depict the improvement in the Read Access Time Operation, Write Access Time Operation, Leakage and Stability of a single bit SRAM cell.

Keywords

CMOS memory circuits; SRAM chips; circuit stability; integrated circuit design; bit line; contemporary CMOS technology; data leakage; data line; data retention; embedded design; low leakage 6T SRAM cell; read access time operation; signal swing reduction; single bit SRAM cell; size 90 nm; stability; static random access memory; word decoding scheme; write access time operation; CMOS integrated circuits; Equations; Mathematical model; Power demand; SRAM cells; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing, Communication and Conservation of Energy (ICGCE), 2013 International Conference on

Conference_Location

Chennai

Type

conf

DOI

10.1109/ICGCE.2013.6823393

Filename

6823393