LVCMOS I/O standard and drive strength based energy efficient design on ultra scale FPGA

In this paper by using Drive Strength techniques and Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) I/O standards, we have designed energy efficient Frequency Meter in Xilinx ISE 14.4 and implemented on -2 speed grade, XC6VLX75T device and virtex-6 FPGA. We have used four different drive strength that is 2mA, 4mA, 6mA and 8mA and we have taken four different types of LVCMOS that includes LVCMOS25, LVCMOS18, LVCMOS15 and LVCMOS12. We observed that while operating this frequency meter at frequencies like 1GHz, 10GHz, 100GHz and 1THz, the I/O power reduction of LVCMOS12 is 30%, 54% and 68% less than LVCMOS15, LVCMOS18 and LVCMOS25 respectively, while the drive strength is taken as 2mA. On 4mA drive strength, the I/O power reduction of LVCMOS12 is 31%, 45% and 68% less than LVCMOS15, LVCMOS18 and LVCMOS25 respectively. When operating this frequency meter with 8mA drive strength and device operating frequency in range of 1GHz-1THz, the I/O power reduction of LVCMOS12 is 32%, 44% and 70% less than LVCMOS15, LVCMOS18 and LVCMOS25 respectively.