Digitally controlled impedance based green design on ultra scale FPGA

In this paper LVDCI, LVDCI_DV2 and HSLVDCI I/O standards are used to make green Fibonacci generator. We have taken 3 classes for each LVDCI, LVDCI_DV2 and HSLVDCI. LVDCI_15 has 53-54% less I/O power requirement than LVDCI_25. We achieve 65-66% power reduction with LVDCI_DV2_15 in compare to LVDCI_DV2_25. In order to achieve energy efficiency along with high performance, when we use high speed variant of LVDCI i.e. HSLVDCI_15 has 55% less I/O Power reduction than HSLVDCI_25 along with significant reduction in time to implement this design. In this work, we are using device operating frequencies in range of 1 GHz-1 THz. This is implemented in verilog on 40 nm ultra scale FPGA. For verification and validation of functionality of Fibonacci generator, we write verilog test fixture and simulate in Isim.