Implementation of 16-bit floating point multiplier using Residue Number system

This paper aims at the implementation of 16 bit floating point multiplier using Residue Number system. Residue Number System (RNS), which is a non-weighted number system gains popularity in the implementation of fast and parallel computing applications. It has inherent properties such as modularity, parallelism and carry free computation, which speeds up the arithmetic computations. Floating Point can be represented as M × B^E where M is Mantissa, E is the Exponent and B is the base. Floating point RNS multiplier consists of RNS Exponent modulo Adder and RNS Mantissa modulo multiplier. In this paper, floating point multiplier will be implemented using Verilog HDL using ModelSim and synthesized using Altera Cyclone II Quartus and frequency of multiplier is found to be 311MHz.