Implementation of non-linear pipelined floating point adder

Floating point addition is a frequently used operation in real time applications and image processing. Its structure is complex due to multiple shifts, addition and normalization units which increase the latency of operation. In order to have the high performance low latency is desired along with higher throughput. In this paper we have used non-linear pipelining concept to divide the adder operation into multiple sub-functional units. The functional units complete their execution in variable time and are dynamically scheduled. This also leads to hardware reutilization. Floating point numbers will be considered in their IEEE754 half precision format [16 bits]: 1bit sign, 5 bit exponent, 10 bit mantissa. The architecture is developed with Verilog HDL and simulated using ALTERA Device EP2C20F484C7.