Error-Rate Estimation Combining SEE Static Cross-Section Predictions and Fault-Injections Performed on HDL-Based Designs

An approach aiming at estimating the error rates of integrated circuits, early in the design phase, is presented. It combines static SBU cross-sections predicted from MUSCA SEP3 (Multi-Scales Single Event Phenomena Predictive Platform) and results of fault-injection performed at netlist level thanks to NETFI method (NETlist Fault Injection). This approach was applied to predict dynamic cross-sections for two different circuits: the 8051 microcontroller and Leon2 processor. The good correlation between predictions and measures puts in evidence the efficiency of the proposed MUSCA SEP3/NETFI approach and tools.