Impact of Temperature Variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study

The paper presents a comprehensive comparison study of p-i-n and p-n-p-n tunnel field-effect transistor (TFET) architectures and the impact of temperature on their dc and circuit performance. The impact of a hetero-gate (HG) dielectric on the circuit performance also forms the part of the study. The device performance of p-i-n and p-n-p-n TFET with high-k dielectric and HG dielectric and the effect of temperature on the drain current characteristics, I_on/I_off, and threshold voltage has been investigated and compared with MOSFET. Furthermore, the variations in the inverter (n-TFET with resistive load) transient characteristics and the fall delay due to temperature variations are studied using mixed mode simulations carried out with ATLAS device simulation software. Results reveal that TFET exhibits weak temperature dependence when the current conduction is band-to-band tunneling dominated, while the temperature dependence increases in the off-state regime, and the fall delay of resistive load n-TFET inverter decreases with increasing temperature.