Eliminating Conflicts in a Multilevel Cache Using XOR-Based Placement Techniques

Eliminating the conflict misses always remained the primary objective for the designers of cache memory. Although many alternative cache block placement techniques have been proposed in the past, the amount of research published on this so far is less than one expects. Most of the past techniques discuss to eliminate conflicts where an application generates a particular memory access pattern in a solo cache memory. With the advent of multiprocessing architectures it becomes more likely that an application mix does not generate a regular access pattern against a multilevel cache hierarchy system. In this paper, we present two cache placement techniques called the least-XOR and the full-XOR specially tailored for a multilevel cache system. These techniques lower the conflict misses by eliminating the conflicts occurring under the scenarios where two addresses are in conflict with each other at multiple levels in a cache hierarchy. Since these schemes target only the cache hashing functions, they do not require any additional hardware on the chip. Our results on sixteen memory intensive spec2000 benchmark traces show that the proposed schemes gives a significant improvement in the cache miss rate, memory traffic and CPI over the traditional scheme. The full-XOR technique achieves 19% reduction whereas least-XOR achieves 17% reduction in the L3 cache global miss rate. The results also show that the schemes perform well even for multi-trace workloads.