DocumentCode
688151
Title
DCP: Improving the Throughput of Asynchronous Pipeline by Dual Control Path
Author
Bo Su ; Li Shen ; Lei Wang ; Zhiying Wang ; Yourui Wang ; Libo Huang ; Wei Shi
Author_Institution
State Key Lab. of High Performance Comput., Nat. Univ. of Defense Technol., Changsha, China
fYear
2013
fDate
13-15 Nov. 2013
Firstpage
230
Lastpage
237
Abstract
Pipeline requires both low latency and high throughput. Synchronous pipeline achieves a near optimized throughput but suffers from the worst-case computation delay. Meanwhile, asynchronous pipeline keeps an optimized computation delay but suffers from the low throughput. In this paper, we present dual control path (DCP), a new structure of four-phase handshake asynchronous control path, to improve the throughput of asynchronous pipeline. We leverage the existing fully decoupled four-phase handshake elements and asymmetric delay elements to found DCP. Experimental results show the asynchronous pipeline with DCP could achieve high throughput as well as low computation delay, only with tiny area overhead.
Keywords
delays; optimisation; pipeline processing; synchronisation; DCP; asymmetric delay elements; asynchronous pipeline improvement; computation delay optimization; dual control path; four-phase handshake asynchronous control path; four-phase handshake elements; synchronous pipeline; worst-case computation delay; Data transfer; Delays; Latches; Pipelines; Registers; Synchronization; Throughput; Asynchronous; Control Path; Pipeline; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing (HPCC_EUC), 2013 IEEE 10th International Conference on
Conference_Location
Zhangjiajie
Type
conf
DOI
10.1109/HPCC.and.EUC.2013.42
Filename
6831924
Link To Document