A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory

The continuing miniaturization of complementary metal oxide semiconductor (CMOS) technology has brought in two critical issues-the high power and long global interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents a new design of the key component in processors-multi-bit full adder, whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RTM). The MTJ sharing technique with demultiplexing approach is used in the proposed non-volatile full adder (NVFA) to greatly reduce the area and power, and improve the speed and sensing margin as well. The proposed NVFA scheme can also apply to the other types of non-volatile memory (NVM). Compared to the state-of-art magnetic full adder (MFA), our proposed NVFA has reduced the power and area by 5.9 times and 50%, respectively. It also accelerates the speed by 10% and increases the sensing margin by more than 66%.