Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects

Author

Kyeong-Jae Lee ; Hyesung Park ; Jing Kong ; Chandrakasan, Anantha P.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA

Volume

60

Issue

1

fYear

2013

fDate

Jan. 2013

Firstpage

383

Lastpage

390

Abstract

We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18-μm CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11× faster speeds and 1.54× lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics.

Keywords

CMOS logic circuits; field programmable gate arrays; integrated circuit interconnections; low-power electronics; monolithic integrated circuits; power integrated circuits; wires (electric); CMOS aluminum wire; double-length line replacement; energy interconnection; four-layer graphene wire; low-capacitance graphene wire; low-swing voltage; monolithically integrated graphene wire interconnection; size 0.18 mum; subthreshold FPGA demonstration; ultralow power electronics; voltage 0.4 V; CMOS integrated circuits; Capacitance; Delay; Field programmable gate arrays; Integrated circuit interconnections; Wires; CMOS integrated circuits; graphene; interconnects;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2012.2225150

Filename

6353910