An efficient RPCT (Reduced Pin Count Testing) based on test data compression using burst clock controller in 3D-IC

Author

Yong Lee ; Sungyoul Seo ; Sungho Kang

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

2013

fDate

17-19 Nov. 2013

Firstpage

176

Lastpage

179

Abstract

RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.

Keywords

automatic test equipment; design for testability; integrated circuit design; integrated circuit testing; system-on-chip; three-dimensional integrated circuits; 3D-IC; ATE channel consumption; ATE dependence; DFT circuitry; SoC development; automatic test equipment; burst clock controller; control block; design-for-test circuitry; efficient-RPCT test method; internal-external clock signal; reduced pin count testing; system-on-chip development; test data compression; testing complexity; Clocks; Decoding; Pins; Synchronization; System-on-chip; Test data compression; Testing; 3D-IC test; burst clock controller; reduce pin count testing; test data compression;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2013 International

Conference_Location

Busan

Type

conf

DOI

10.1109/ISOCC.2013.6863965

Filename

6863965