Three-dimensional pipeline clock network design with multi-layer processor chip and multi-clock VLSI system

This paper proposes the pipeline clock network design for recent three-dimensional (3D) VLSI system. The multi-layer processor chip can be connected by Through-Silicon Via (TSV) tunnels. The multi-clock VLSI system can also enhance whole VLSI system performance for better design flexibility. The pipeline clock network is determined by inserted buffer control. Different size buffers in different layers can realize fast system operation and zero-skew clock signals. Whole VLSI processor speed can be increased rapidly, and 3D chip size can also be reduced greatly by 3D pipeline clock network design. System clock routing efficiency can also be improved because 3D clock tree can avoid most parts of the obstacle elements. Experimental results can be used to prove that 3D pipeline clock network has better performance with fast operation speed and small routing length. VLSI system power can be reduced because of minimal routing distance in 3D network design.