Clocked CMOS adiabatic logic with low-power dissipation

This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.