• DocumentCode
    692604
  • Title

    High-speed binary to binary-coded-decimal converters for decimal multiplications

  • Author

    Tso-Bing Juang ; Yu-Ming Chiu

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Pingtung Inst. of Commerce, Pingtung, Taiwan
  • fYear
    2013
  • fDate
    17-19 Nov. 2013
  • Firstpage
    370
  • Lastpage
    371
  • Abstract
    In this paper, we have proposed high-speed binary to binary-coded-decimal (BCD) converters for decimal multiplications. By employing new recoding methods, our proposed converters can perform high-speed conversions from binary numbers to decimal outputs. Synthesis results show that our proposed converters can achieve over 66% delay and 0.8% area reduction compared with previous proposed method, respectively. Our proposed converters can be applied to decimal multiplications to boost the performance.
  • Keywords
    adders; binary codes; digital arithmetic; logic circuits; area reduction; binary numbers; decimal multiplication; decimal outputs; delay reduction; high-speed binary-BCD converters; high-speed binary-to-binary-coded-decimal converters; high-speed conversions; recoding method; Adders; Computer architecture; Delays; Floating-point arithmetic; Hardware; Logic gates; Very large scale integration; Computer Arithmetic; Decimal additions; Decimal multiplications; VLSI;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2013 International
  • Conference_Location
    Busan
  • Type

    conf

  • DOI
    10.1109/ISOCC.2013.6864053
  • Filename
    6864053