A 400nW CMOS bandgap voltage reference

A resistorless 400 nano-Watts bandgap voltage reference in standard 0.25μ digital CMOS process is presented. Parasitic vertical bipolar transistors (BJT) are used to generate a series of cascaded thermal voltages (V_T), which is summed with a base-emitter voltage (V_BE) to produce a ~1.25V bandgap voltage (V_BG). Statistical contributions of CMOS amplifiers´ inherent random noise, offset, and drift terms to the V_BG are not multiplied but rather accumulated by the square root of number of additions, fundamentally because the proposed configuration uses summation and not multiplication to generate the bandgap´s proportional to absolute temperature (PTAT) term. Such a bandgap can operate at ultra-low currents (i.e. nano-amperes) without using (large size) resistors, which saves significant die area. This design does not require special transistors, and it does not stack parasitic BJTs that could impose V_DD headroom constraints. Furthermore, the design does not use multi-staged (special hybrid or) CMOS voltage followers with built-in offset voltage to generate pseudo-PTAT voltage. Therefore, manufacturability and portability across different process nodes at standard CMOS foundries is optimized. Monte Carlo simulations and analysis demonstrates that a temperature coefficient (TC) of about ±50 ppm/°C over a 200°C temperature range can be achievable, and voltage coefficient of about ±0.2% / V with VDD spanning 1.5V to 4.5V can be realized.