FPGA implementation of a modified advanced encryption standard algorithm

In this paper, a method to improve the security level of advanced encryption standard (AES) algorithm is proposed. The proposed algorithm, which is based on the standard AES, increases the complexity of the encryption process leading to a more difficultness against attacking and decryption of the plaintext without using the correct encryption key. The research investigates the AES algorithm with regard to Field Programmable Gate Array (FPGA) and the Very High Speed Integrated Circuit Hardware Description Language (VHDL). ModelSim-Altera Starter Edition Software for Quartus II is used for simulation and optimization of the structural VHDL code. All the required transformations of the encryption and decryption processes are done using a pipelined cyclic design method to minimize hardware consumptions. The pipelined design is implemented on Altera Cyclone IV family of FPGA devices and a good throughput is achieved with minimal area.