FPGA implementation of RANSAC algorithm for real-time image geometry estimation

Author

Jia Wei Tang ; Shaikh-Husin, N. ; Sheikh, Usman Ullah

Author_Institution

VeCAD Res. Lab., Univ. Teknol. Malaysia, Skudai, Malaysia

fYear

2013

fDate

16-17 Dec. 2013

Firstpage

290

Lastpage

294

Abstract

Random Sample Consensus (RANSAC) is commonly used in many estimation tasks especially in computer vision applications due to its simplicity. This paper presents a hardware/software co-design implementation of RANSAC algorithm for real-time affine geometry estimation on a field programmable gate array (FPGA) platform. Double buffering technique is used to store and process data in pipeline. Experimental result shows that the proposed system managed to speed up the software process by about 11.4 times for 100 data points. The proposed architecture was also tested on Altera DE2-115 with 100 MHz NiosII Processor running to handle a video stream of 30 frames per second.

Keywords

buffer storage; computer vision; field programmable gate arrays; hardware-software codesign; random processes; sampling methods; Altera DE2-115; FPGA; NiosII Processor; RANSAC algorithm; computer vision applications; data process; data store; double buffering technique; field programmable gate array; hardware/software co-design implementation; random sample consensus; real-time image geometry estimation; software process; video stream; Estimation; Field programmable gate arrays; Geometry; Hardware; Real-time systems; Software; Software algorithms; FPGA; RANSAC; embedded hardware system; image geometry estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Research and Development (SCOReD), 2013 IEEE Student Conference on

Conference_Location

Putrajaya

Type

conf

DOI

10.1109/SCOReD.2013.7002592

Filename

7002592