Microarchitectural-level statistical timing models for near-threshold circuit design

Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper proposes architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.