DocumentCode :
695313
Title :
Automatic timing-coherent transactor generation for mixed-level simulations
Author :
Li-Chun Chen ; Hsin-I Wu ; Ren-Song Tsay
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
fYear :
2015
fDate :
19-22 Jan. 2015
Firstpage :
588
Lastpage :
593
Abstract :
In this paper we extend the concept of the traditional transactor, which focuses on correct content transfer, to a new timing-coherent transactor that also accurately aligns the timing of each transaction boundary so that designers can perform precise concurrent system behavior analysis in mixed-abstraction-level system simulations which are essential to increasingly complex system designs. To streamline the process, we also developed an automatic approach for timing-coherent transactor generation. Our approach is actually applied in mixed-level simulations and the results show that it achieves 100% timing accuracy while the conventional approach produces results of 25% to 44% error rate.
Keywords :
electronic design automation; mixed analogue-digital integrated circuits; automatic timing-coherent transactor generation; correct content transfer; mixed-abstraction-level system simulations; mixed-level simulations; Clocks; Coherence; Data models; Delays; Payloads; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
978-1-4799-7790-1
Type :
conf
DOI :
10.1109/ASPDAC.2015.7059072
Filename :
7059072
Link To Document :
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