• DocumentCode
    695319
  • Title

    Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning

  • Author

    Shao-Yun Fang ; Yi-Shu Tai ; Yao-Wen Chang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
  • fYear
    2015
  • fDate
    19-22 Jan. 2015
  • Firstpage
    671
  • Lastpage
    676
  • Abstract
    Self-aligned double patterning (SADP) has become a preferred double patterning technology, due to its better overlay controllability. Two types of layout decomposition schemes are used to define two-dimensional layout patterns in SADP: Spacer-is-Metal (SIM) and Spacer-is-Dielectric (SID), and SIM-type layout decomposition typically has higher decomposition flexibility (especially for gridless designs). While SID-type layout decomposition has been studied extensively, however, only one previous work extended a satisfiability-based SID-type decomposer to SIM-type layout decomposition; this SAT-based method is inefficient for large-scale designs and not applicable to non-decomposable layouts. This paper introduces an efficient graph-based SIM-type layout decomposition heuristic. The decomposition problem is first transformed into a constrained set-covering problem. Then, an efficient algorithm composed of a greedy heuristic followed by a partition-based solution refinement scheme is proposed to simultaneously minimize the conflicts on both core masks and cut masks. Experimental results show that the algorithm can efficiently derive a good decomposition solution with minimized pattern conflicts.
  • Keywords
    graph theory; integrated circuit layout; lithography; masks; set theory; SADP; SID-type layout decomposition; constrained set-covering problem; core masks; cut masks; decomposition flexibility; double patterning technology; graph-based SIM-type layout decomposition heuristic; greedy heuristic; layout decomposition schemes; overlay controllability; partition-based solution refinement scheme; satisfiability-based SID-type decomposer; self-aligned double patterning; spacer-is-dielectric; spacer-is-metal; two-dimensional layout patterns; Algorithm design and analysis; Heuristic algorithms; Law; Layout; Merging; Partitioning algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific
  • Conference_Location
    Chiba
  • Print_ISBN
    978-1-4799-7790-1
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2015.7059085
  • Filename
    7059085