An 8 Bit 4 GS/s 120 mW CMOS ADC

Author

Hegong Wei ; Peng Zhang ; Sahoo, B.D. ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA

Volume

Issue

fYear

2014

fDate

Aug. 2014

Firstpage

1751

Lastpage

1761

Abstract

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; delay lines; CMOS ADC; digital background calibration technique; high resolution variable delay line; interchannel timing mismatches; pipelined time interleaved channels; power 120 mW; size 65 nm; time interleaved ADC; timing mismatch detection algorithm; Bandwidth; CMOS integrated circuits; Calibration; Clocks; Convergence; Jitter; Timing; Analog-to-digital conversion; interleaving; pipelined analog-to-digital converter (ADC); time error detection and correction; timing calibration; variable delay lines;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2313571

Filename

6784501

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=69904