Low-latency and high-efficiency bit serial-serial multipliers

A new bit serial-serial multiplier for unsigned numbers is presented in this paper. The numbers being multiplied enter the circuit simultaneously in LSB first bit-serial form. The multiplier is of immediate response, pipelined at the bit level and has small combinational delay. A variation of this multiplier that operates with 100% efficiency, namely it does not require zero bits to be inserted between successive input data words, produces the product in full-precision is also proposed. The proposed schemes are well suited for DSP applications, compared with other schemes exhibit superior performance in terms of hardware complexity and throughput.