FPGA-based implementation of a real-time 5000-word continuous speech recognizer

We have developed a hidden Markov model based 5000-word speaker independent continuous speech recognizer using a Field-Programmable Gate Array (FPGA). The feature extraction is conducted in software on a soft-core based CPU, while the emission probability computation and the Viterbi beam search are implemented using parallel and pipelined hardware blocks. In order to reduce the bandwidth requirement to external DRAM, we employed bit-width reduction of the Gaussian parameters, multi-block computation of the emission probability, and two-stage language model pruning. These optimizations reduce the memory bandwidth requirement for emission probability computation and inter-word transition by 81% and 44%, respectively. The speech recognition hardware was synthesized for the Virtex-4 FPGA, and it operates at 100MHz. The experimental result on Wall Street Journal 5k vocabulary task shows that the developed system runs 1.52 times faster than real-time.