Method for efficient flash bit cell current compression in deeply erased bits

Embedded flash endurance and data retention are the key reliability concerns for numerous microcontroller applications. Consumers require memory endurance on the order of 10⁶ to 10⁷ cycles and storage life of greater than a decade. In order to manufacture reliable products screens must be developed that are capable of testing for end of life (EOL) conditions while the bits are in a fresh or uncycled state. Manufacturing reliability tests are based upon the concept of observing the bit cell current (BCC) or threshold voltage (VT) of the distribution of bits before and after stress conditions. However the spread in distributions of BCCs and VTs in a flash bank can vary widely on uncycled parts. These wide distributions are a result of deeply erased bits. They can prevent successful screening of deviant bits as stress conditions fail to move failing bits out of the distribution of good bits. This paper presents a manufacturable method for compressing erased bits into a tight distribution to allow for short duration stresses to successfully screen deviant bits.