Title :
Improved pipeline data flow for DySER-based platform
Author :
Hou Zijian ; Chen Xin ; He Weifeng
Author_Institution :
Tongji Univ., Shanghai, China
Abstract :
The coarse-grained reconfigurable architecture(CGRA) has advantages over the traditional FPGAs in terms of delay, area and configuration time. DySER is a novel architecture of the CGRA, which can support both functionally specialization and parallelism specialization. In this paper, the relationship between the bandwidth, data transmission time and RC array scale of DySER-based platform have been analyzed. To improve the architecture, we also present a new data transmission mode called incomplete three-phase pipeline. Compared with the original platform, the results show that the improved platform increases the whole time efficiency by 11% to 15%.
Keywords :
field programmable gate arrays; pipeline processing; reconfigurable architectures; CGRA; DySER-based platform; FPGA; RC array scale; coarse-grained reconfigurable architecture; data transmission mode; data transmission time; functionally specialization; incomplete three-phase pipeline; parallelism specialization; Arrays; Bandwidth; Data communication; Optimization; Parallel processing; Pipelines; DySER; Reconfigurable system; computing flow; pipeline; reconfigurable cell;
Conference_Titel :
Quality Electronic Design (ISQED), 2015 16th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-7580-8
DOI :
10.1109/ISQED.2015.7085413
