Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies

FinFET devices are considered to be the device substitute for bulk CMOS in sub-20nm technology nodes due to the reduced short-channel effects, improved ON/OFF current ratio, and improved voltage scalability. This paper investigates the problem of optimal selection of deeply-scaled FinFET technology to achieve minimum energy consumption for different applications such as sensor applications, smartphones, embedded micro-processors, or server micro-processors, which differ in the required performance and duty ratio. For each application space, different FinFET technologies (with different V_th and gate length biases) are compared in term of minimum energy consumption for both logic circuits and cache memories. A device-circuit-architecture cross-layer framework has been developed to facilitate this technology selection. This optimal technology selection procedure demonstrates up to 11× energy saving compared to poorly selected technologies.