Separation of concerns for hardware components of embedded systems in BIP

Memory-based concerns such as Design-for-test, logic built in self test, memory technology mapping and clock division concerns traditionally happen at circuit-level and require team-months of verification time. We present a novel hardware concern-based methodology for embedded system frameworks that enables automatic separation of memory based hardware concerns at high-level where verification is easier. The methodology relies on a conservative memory inference transformation that separates sequential from combinational elements. We developed a tool that automatically performs the transformation for BIP, an open source embedded systems design framework. It takes entry BIP model code and outputs BIP model code where memory elements are separated from the rest of the logic. We evaluated our method with three BIP case studies. Our results show that our method enabled designers to identify and fix injected defects at the BIP level, where they are more comfortable, in reasonable time without the need to dive into the circuitry that is highly coupled with concerns.