A scheme for the VLSI implementation of FIR digital filters with reduced latency

A modular bit-parallel implementation scheme for an FIR digital filter which is systolic in the bit-level and exhibits a latency of three clock cycles, is presented. In the word-level, the scheme is that of the merged two-way pipeline systolic array in which each processing element computes two product terms and adds them to a partial sum. In this way high throughput and immediate response are obtained. Merging is also used in the bit-level for the realization of the processing elements in order to obtain low latency. Moreover, the cells of the processing elements are internally pipelined which gives high operation rate, limited by the propagation delay of a gated full-adder and a latch.